The present invention relates to a semiconductor memory device and, more particularly, relates to a semiconductor memory device including at least one redundancy memory array therein.
A semiconductor memory device is mainly comprised of many memory cells arranged along both rows and columns in an orthogonal fashion. Each of the memory cells stores a respective bit of data. Each bit of data to be written or read is located at a corresponding memory cell which is specified by an address information. The address information determines both a row address and a column address so that the desired one of the memory cells can be accessed at the intersect portion of both the determined row and column addresses.
Generally, an undesired defect is often created in one of the great number of memory cells, during the manufacturing process of the memory device. It is, of course, obvious that the memory device cannot operate normally when the memory device includes such a defective memory cell therein. Therefore, such a memory device cannot be put into practical use, and such a memory device must be left out. However, it is not preferable, from an economical point of view, to leave out the manufactured memory device due to the presence of only one defective memory cell among a great number of memory cells.
In order to save such a defective memory device, the redundancy memory array is usually incorporated with the main memory cells. When said address information specifies a row memory array or a column memory array, including the defective memory cell, such defective row or column memory array is replaced by the redundancy memory array which contains a corrected memory cell with regard to the defective memory cell of the main memory cells.
A conventional semiconductor memory device, including such a redundancy memory array, is comprised of the main memory cells, an addressing means for specifying both the row memory array and the column memory array of the main memory cells, a detecting means for detecting whether or not the addressing means specifies the row or column memory array including the defective memory cell therein and a switching means for replacing the specified row or column memory array by the redundancy memory array, according to the result of the detecting means. Above all, the present invention refers specifically to an improvement of the switching means and the switching procedure. In the above mentioned conventional semiconductor memory device, first, the detecting means is activated for inspecting the address information to be applied to the addressing means, but, the addressing means is not yet activated; second, if the detecting means determines that the address information does not specify the row or column memory array including the defective memory cell, the addressing means starts being activated and accesses the specified memory cell; alternatively, if the detecting means determines that the address information specifies the row or column memory array, including the defective memory cell, the addressing means is not yet activated, but, the switching means activates the redundancy memory array in place of the defective memory array of the main memory cells and; last, the output data to be read is produced from the specified memory cell to a data output buffer circuit via a data bus or, if necessary, the input data to be written is supplied from a data input buffer circuit to the specified memory cell via the data bus.
Thus, the above mentioned memory device of the prior art has a shortcoming, in that the access time for reading or writing the data is long, and accordingly a high speed operation of the semiconductor memory device cannot be expected. This is because, a time for inspecting the address information, by means of the detecting means, must be inserted prior to each time the accessing operation for the main memory cells is carried out.